Principal Design Engineer- Memory Ip

Cadence

Base: $154,000 to $286,000 (california); bonus/equ...
Proficiency in logic design and micro-architecture
Experience with verilog/systemverilog simulation
Knowledge of ic design for high speed and low power
The role requires proficiency in logic design, micro-architecture, and IC design with a focus on high speed and low power

Job Summary

  • The role requires proficiency in logic design, micro-architecture, and IC design with a focus on high speed and low power.
  • Candidates must have at least six years of experience in digital IC development projects and demonstrate strong communication skills.
  • The position offers competitive compensation including bonus, equity, and comprehensive benefits like medical, dental, vision, and 401(k) matching.

Matching Summary

The role requires proficiency in logic design, micro-architecture, and IC design with a focus on high speed and low power.

Salary

Base: $154,000 to $286,000 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, holidays, 401(k) match, stock purchase plan, medical/dental/vision

Skills & Requirements

Must-have

  • Proficiency in logic design and micro-architecture
  • Experience with Verilog/SystemVerilog simulation
  • Knowledge of IC design for high speed and low power
  • Familiarity with JEDEC-DDR and DFI protocols
  • Memory IP design experience

Nice-to-have

  • Excellent verbal and written communication skills
  • Ability to lead and contribute in a cooperative team
  • Strong leadership and innovation mindset

Key Requirements

  • BS degree with 8+ years applicable experience
  • MS degree with 6+ years applicable experience
  • Degree in electrical engineering, microelectronics, or solid state physics
  • Good communication skills in English

Work Rights

Not specified

Tailored Resume

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