Bachelor's degree in computer or electrical engineering
Systemverilog and uvm testbench development
Functional verification flow for digital soc ips
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Cadence Design Systems Inc. is seeking a Design Engineer II for Digital Design Verification in Campinas, Brazil. The role involves collaborating with teams to develop functional verification flows for digital SoCs, utilizing Cadence's advanced technologies.
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Job Summary
This role involves developing the entire functional verification flow on digital SoC IPs according to customer technical needs.
The successful candidate will work with an experienced team to implement SoC designs in advanced process nodes using market-leading technologies.
Cadence offers competitive benefits, hybrid work options, and is recognized as a Great Place to Work globally.
Matching Summary
Match Score: 75
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Cadence Design Systems Inc. is seeking a Design Engineer II for Digital Design Verification in Campinas, Brazil. The role involves collaborating with teams to develop functional verification flows for digital SoCs, utilizing Cadence's advanced technologies.
**
Skills & Requirements
Must-have
Bachelor's degree in Computer or Electrical Engineering
SystemVerilog and UVM testbench development
Functional verification flow for digital SoC IPs
Code and functional coverage analysis
English verbal and written communication skills
Nice-to-have
Experience with formal verification methodologies
Knowledge of Cadence verification tools like XCelium
Effective cross-team communication and documentation
Key Requirements
Complete Bachelor's degree in Computer or Electrical Engineering
Ability to verify digital modules autonomously in subsystem/SOC context
Solid experience in SystemVerilog, UVM, and C/C++
Proficiency in debugging SystemVerilog and UVM-based testbenches