Senior Physical Design Integration Engineer

Intel Retiree Medical Plan Trust

Folsom, California, US
Base: $256,050.00-361,480.00 usd; bonus/equity: st...
Hybrid
Rtl to gds implementation
Synthesis, place and route
Static timing analysis
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc

Job Summary

  • The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.
  • We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc.

Salary

Base: $256,050.00-361,480.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • RTL to GDS implementation
  • Synthesis, place and route
  • Static timing analysis
  • Power/clock distribution analysis
  • Formal equivalence verification
  • Layout verification, ERC, DRC

Nice-to-have

  • Leadership and communication skills
  • EDA vendor collaboration
  • Methodology and flow automation development

Key Requirements

  • Bachelor's in EE/CE + 15 years experience
  • Master's in EE/CE + 12 years experience
  • Experience in logic design, VLSI/ASIC design
  • Experience with Unix/Linux, Perl, TCL

Work Rights

Not specified

Tailored Resume

Cover Letter