Verification Engineer

Altera Digital Health

New Delhi, India
Fully remote
Systemverilog and uvm
Verification environments
Constrained-random verification
Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients

Job Summary

  • Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
  • Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
  • Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.

Matching Summary

Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • verification environments
  • constrained-random verification
  • assertion-based verification
  • coverage-driven verification
  • Python or Perl scripting

Nice-to-have

  • collaborative cross-functional team
  • technical reviews
  • problem-solving skills
  • analytical skills

Key Requirements

  • 3+ years ASIC or FPGA design verification
  • Bachelor's or Master's degree
  • Verilog or VHDL expertise
  • SystemVerilog expertise
  • UVM-based testbenches experience

Work Rights

Not specified

Tailored Resume

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