Analog Mixed-signal Layout Intern

Astera Labs

Singapore, Singapore
On-site
Analog mixed-signal layout
Lvs, drc, pex
Layout best practices
Astera Labs is looking for an Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. The position offers hands-on experience with advanced technology nodes and collaboration with experienced engineers, while encouraging applications from diverse backgrounds

Job Summary

  • Assist in the design and layout of high-performance analog and mixed-signal IP blocks.
  • Perform layout-vs-schematic (LVS), design-rule checks (DRC), and parasitic extraction (PEX) to ensure design quality and manufacturability.
  • Gain hands-on experience with real design projects leading to tape-out and mentorship from experienced engineers.

Matching Summary

Match Score: 85

Astera Labs is looking for an Analog Mixed-Signal Layout Intern to assist in the design and layout of high-performance analog and mixed-signal IP blocks. The position offers hands-on experience with advanced technology nodes and collaboration with experienced engineers, while encouraging applications from diverse backgrounds.

Skills & Requirements

Must-have

  • Analog Mixed-Signal Layout
  • LVS, DRC, PEX
  • Layout best practices
  • EDA tools (Cadence, Synopsys, Mentor)

Nice-to-have

  • Version control systems
  • CMOS, FINFET devices
  • High-speed analog design

Key Requirements

  • Bachelor's or Master's in Electrical Engineering or related field
  • Basic understanding of analog/mixed-signal IC design
  • Familiarity with EDA tools
  • Basic understanding of matching techniques and layout symmetry

Work Rights

Not specified

Tailored Resume

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