NXP Semiconductors is seeking a Senior Static Timing Analysis (STA) Engineer for their IC design team in Tianjin, China. The role focuses on leading timing signoff activities for complex SoC projects and requires extensive experience in static timing analysis and collaboration with design teams
Job Summary
This role will lead timing signoff activities for complex SoC projects, ensuring robust timing closure across multiple process, voltage, and temperature corners.
Own full-chip static timing analysis and signoff for advanced-node SoC designs.
Provide technical leadership in methodology development, tool evaluation, and flow automation.
Matching Summary
Match Score: 85
NXP Semiconductors is seeking a Senior Static Timing Analysis (STA) Engineer for their IC design team in Tianjin, China. The role focuses on leading timing signoff activities for complex SoC projects and requires extensive experience in static timing analysis and collaboration with design teams.
Skills & Requirements
Must-have
Static Timing Analysis (STA)
timing signoff activities
STA constraints (SDC)
timing methodologies
debug timing violations
timing optimization
timing models validation
cross-functional collaboration
technical leadership
scripting skills (Tcl, Perl, Python, Shell)
Nice-to-have
mentor junior engineers
tool evaluation
flow automation
Key Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on STA experience
Proficiency with Synopsys PrimeTime or Cadence Tempus
Solid understanding of OCV/AOCV/POCV, clock tree synthesis, crosstalk, MCMM flows
Familiarity with synthesis, place-and-route, and ECO flows
Expertise with SDC constraints and timing debugging