You will be a key member of the Silicon One development organization collaborating closely with Front-end RTL and backend physical design teams
Job Summary
You will be a key member of the Silicon One development organization collaborating closely with Front-end RTL and backend physical design teams.
Your primary focus will be to drive high-quality Design for Test (DFT) verification ensuring robust and reliable silicon solutions that meet Cisco's standards.
The role involves taking part in all aspects of digital design from micro-architecture to RTL design and qualification within a hybrid work model.
Matching Summary
You will be a key member of the Silicon One development organization collaborating closely with Front-end RTL and backend physical design teams.
Skills & Requirements
Must-have
5+ years ASIC digital design experience
Proficient in Verilog/SystemVerilog coding
Experience with AMBA protocols AXI APB AHB
Scripting skills in Python Tcl Make
Front-end tool knowledge simulators linting
Nice-to-have
Familiarity with power optimization techniques
Knowledge of UPF power intent
Experience with DFT/MBIST methodologies
Strong communication and self-motivation
Cross-functional collaboration skills
Key Requirements
5+ years industry experience in ASIC digital design