Senior Pdk Engineer

NVIDIA

Base: $168,000 - $264,500 (level 4) or $196,000 - ...
Hybrid
Strong electrical engineering background
In-depth understanding of circuits and layouts
Experience in drc/lvs and hspice
NVIDIA is seeking a Senior PDK Engineer to join its Advanced Technologies Group, focusing on aligning PDK development with foundry partners and managing CAD-related tasks. The ideal candidate should possess a strong electrical engineering background, with significant experience in VLSI design and proficiency in PDK-related processes

Job Summary

  • The role involves aligning the PDK development plan with foundry partners based on NVIDIA's test chip and product tapeout schedules.
  • Candidates must possess a strong electrical engineering background with an in-depth understanding of circuits, layouts, and VLSI design.
  • NVIDIA offers competitive base salary ranges from $168,000 to $310,500 depending on level, along with equity and benefits.

Matching Summary

Match Score: 85

NVIDIA is seeking a Senior PDK Engineer to join its Advanced Technologies Group, focusing on aligning PDK development with foundry partners and managing CAD-related tasks. The ideal candidate should possess a strong electrical engineering background, with significant experience in VLSI design and proficiency in PDK-related processes.

Salary

Base: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5); Bonus/Equity: Eligible for equity; Benefits: Comprehensive benefits package included

Skills & Requirements

Must-have

  • Strong electrical engineering background
  • In-depth understanding of circuits and layouts
  • Experience in DRC/LVS and HSPICE
  • Knowledge of RC extraction and EM analysis
  • Understanding of PDK structure and processes

Nice-to-have

  • Experience in analog and digital IP design
  • Strong interpersonal and communication skills
  • Passion for providing excellent support
  • Creative and autonomous engineer mindset

Key Requirements

  • B.S. in Electrical Engineering with 10 years experience
  • M.S. in Electrical Engineering with 7 years experience
  • Background in MOSFET device behavior and CMOS layout

Work Rights

Not specified

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