Staff, Design For Test Engineer (dft)

Tenstorrent

Bengaluru, India
Hybrid
Dft features into rtl using verilog
Atpg and test coverage analysis
Jtag, scan compression, asst implementation
Tenstorrent is seeking a Design for Test (DFT) Engineer for their Bengaluru office to work on high-performance AI/ML architectures. The role involves implementing DFT features, collaborating with experienced engineers, and contributing to the development of cutting-edge technology in a dynamic environment

Job Summary

  • The role is Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures.
  • Responsibilities include implementation of DFT features into RTL, ATPG and test coverage analysis, and support for silicon bring-up and debug.
  • We welcome candidates at various experience levels for this role, with offers aligning to assessed level during the interview process.

Matching Summary

Match Score: 85

Tenstorrent is seeking a Design for Test (DFT) Engineer for their Bengaluru office to work on high-performance AI/ML architectures. The role involves implementing DFT features, collaborating with experienced engineers, and contributing to the development of cutting-edge technology in a dynamic environment.

Skills & Requirements

Must-have

  • DFT features into RTL using Verilog
  • ATPG and test coverage analysis
  • JTAG, Scan Compression, ASST implementation
  • Gate level simulation
  • MBIST planning, implementation, verification
  • DFx flows and methodology

Nice-to-have

  • Collaborative team environment
  • Passion for AI
  • Solving hard problems
  • Silicon bring-up and debug support

Key Requirements

  • 5+ years industry experience in advanced DFx techniques
  • DFx experience in finFET technologies
  • Experience with industry standard ATPG and DFx CAD tools
  • Familiarity with SystemVerilog and UVM
  • RTL coding for DFx logic
  • Understanding of low-power design flows
  • Knowledge of fault models

Work Rights

Not specified

Tailored Resume

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