Sr Principal Product Engineer

Cadence

Bangalore, India
Soc verification methodology
Systemverilog and uvm
Constrained-random verification
This role sits at the intersection of verification methodology, system architecture, and EDA product engineering

Job Summary

  • This role sits at the intersection of verification methodology, system architecture, and EDA product engineering.
  • You will work directly with advanced verification teams at major semiconductor companies to deploy Portable Stimulus (PSS) in real production environments and help drive the evolution of Perspec.
  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

Matching Summary

This role sits at the intersection of verification methodology, system architecture, and EDA product engineering.

Skills & Requirements

Must-have

  • SoC verification methodology
  • SystemVerilog and UVM
  • constrained-random verification
  • system-level test generation
  • debugging complex verification environments
  • C/C++/Python programming skills

Nice-to-have

  • AI-assisted verification workflows
  • collaboration with R&D
  • software-driven verification
  • emulation and virtual platforms
  • teamwork and collaboration skills

Key Requirements

  • 12+ years of experience
  • MS or BE/BTech degree
  • embedded / bare metal environments experience
  • work authorization not specified

Work Rights

Not specified

Tailored Resume

Cover Letter