Sr. Principle Dft Engineer

NXP

Pune, India
Mentor/synopsys test generation tools
Dft architecture and instrument insertion
Collaboration with soc and dv teams
As a Pune MCU team DFT lead, this candidate needs to architect DFT design and oversee DFT instrument insertion and simulation

Job Summary

  • As a Pune MCU team DFT lead, this candidate needs to architect DFT design and oversee DFT instrument insertion and simulation.
  • The role requires collaboration with SOC leads, IP designers, DV teams, backend leads, and test engineers to ensure successful DFT implementation and silicon bring-up.
  • The candidate will provide guidance to junior DFT engineers and define DFT structures and methodologies including scan, MBIST, JTAG, and functional testing.

Matching Summary

As a Pune MCU team DFT lead, this candidate needs to architect DFT design and oversee DFT instrument insertion and simulation.

Skills & Requirements

Must-have

  • Mentor/Synopsys test generation tools
  • DFT architecture and instrument insertion
  • Collaboration with SOC and DV teams
  • DFT modes STA and IR drop analysis
  • Test pattern bring-up on silicon
  • Guidance to junior DFT engineers

Nice-to-have

  • Experience with synthesis and STA flows
  • Familiarity with Tessent shell flow
  • Lab and test floor debug experience
  • Yield estimation and test optimization
  • DFT AI mindset

Key Requirements

  • BS/MS in Electrical or Computer Engineering
  • 12+ years of DFT experience
  • DFT lead experience for complex SOCs
  • Strong knowledge of JTAG, ATPG, scan compression, IEEE 1500, MBIST, LBIST, SSN

Work Rights

Not specified

Tailored Resume

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