Asic/fpga Design Engineer

Intel Retiree Medical Plan Trust

Penang, Malaysia
Not specified; not specified; not specified
Hybrid
5+ years rtl/logic design experience
Verilog or system verilog coding skills
Fpga ip block development expertise
The role involves developing and maintaining RTL designs for FPGA and ASIC solutions using Verilog or System Verilog

Job Summary

  • The role involves developing and maintaining RTL designs for FPGA and ASIC solutions using Verilog or System Verilog.
  • Candidates must possess strong analytical abilities to debug design issues and collaborate with architects and verification engineers.
  • This position offers a hybrid work model allowing employees to split time between on-site and off-site locations in Penang, Malaysia.

Matching Summary

The role involves developing and maintaining RTL designs for FPGA and ASIC solutions using Verilog or System Verilog.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • 5+ years RTL/Logic design experience
  • Verilog or System Verilog coding skills
  • FPGA IP block development expertise

Nice-to-have

  • Experience with agentic AI technologies
  • Knowledge of packet-based protocols like PCIe
  • Leadership experience managing designer teams

Key Requirements

  • Minimum 5 years of industry experience
  • Demonstrable logic design and RTL writing capability
  • Proficiency with internal and third-party design tools

Work Rights

Not specified

Tailored Resume

Cover Letter