2026 Campus - Soc Backend Design Engineer

NXP Semiconductors

Tianjin, China
Rtl synthesis to gds implementation
Timing convergence (sta)
Physical verification
The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design

Job Summary

  • The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design.
  • The individual is responsible from RTL synthesis to GDS implementation and optimization of design including floor planning, routing, timing convergence (STA) including related design ECO and physical verification for fulfilling all Technology & reliability related rules, such as DRC/LVS/Electromigration/IR drops.
  • Contributes to define best Physical design strategy per technology node.

Matching Summary

The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design.

Skills & Requirements

Must-have

  • RTL synthesis to GDS implementation
  • timing convergence (STA)
  • physical verification
  • DRC/LVS/Electromigration/IR drops
  • Script coding ability Perl/TCL/Python
  • Linux/Unix environment

Nice-to-have

  • Excellent communication skills
  • collaboration spirit
  • SoC design experience

Key Requirements

  • Master degree in microelectronics, electronic engineering, computer science or relevant disciplines
  • Backend SoC design experience is a plus

Work Rights

Not specified

Tailored Resume

Cover Letter