Design Verification Engineer

Altera Corporation

Bengaluru, Karnataka, India
Systemverilog and uvm
Constrained-random verification environments
Coverage-driven verification
You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip)

Job Summary

  • You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip).
  • Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM.
  • Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.

Matching Summary

You will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip).

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • constrained-random verification environments
  • coverage-driven verification
  • assertion-based verification
  • simulation and debug tools
  • Python or Perl scripting

Nice-to-have

  • industry-standard protocols
  • collaborative, cross-functional team environment

Key Requirements

  • 7+ years of experience in ASIC or FPGA design verification
  • Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field
  • Expertise in Verilog or VHDL and SystemVerilog
  • Strong hands-on experience in developing UVM-based testbenches
  • Proficiency in modern verification methodologies
  • Strong scripting skills in Python, Perl, or Tcl
  • Excellent analytical, problem-solving, and debugging skills

Work Rights

Not specified

Tailored Resume

Cover Letter