Job Summary

• Performs Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and Subsystem level.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area.

Matching Summary

Salary

Base: $127,400 - $184,400 USD; Bonus/Equity: Incentive opportunities; Benefits: Not specified

Skills & Requirements

Key Requirements

• Bachelor's degree in computer engineering, electronic Engineering or related field
• 5+ years of relevant experience
• Multiple tape-out experience in deep submicron process nodes
• Extensive knowledge and hands-on experience in physical design flow and EDA tools
• Extensive knowledge and hands-on experience in physical design signoff flow (STA, LEC, ERC, DRC)
• Hardware description languages (VHDL, Verilog)

Work Rights