Principal Software Engineer - Low Power Verification
Cadence
San Jose, California, US
Base: $136,500 to $253,500 annually; bonus/equity:...
C++ development proficiency
Upf (unified power format) implementation
Palladium and protium platform experience
This role involves driving innovations to improve the debuggability, performance, and scalability of multi-billion-gate UPF designs across modular compilation flows
Job Summary
This role involves driving innovations to improve the debuggability, performance, and scalability of multi-billion-gate UPF designs across modular compilation flows.
The successful candidate will collaborate closely with R&D, Product Engineering, and Application Engineering to deploy UPF solutions across diverse flows including AVIP and Dielets.
Candidates are eligible for incentive compensation including bonus, equity, and a comprehensive benefits package featuring 401(k) matching and stock purchase plans.
Matching Summary
This role involves driving innovations to improve the debuggability, performance, and scalability of multi-billion-gate UPF designs across modular compilation flows.
Salary
Base: $136,500 to $253,500 annually; Bonus/Equity: Eligible for incentive compensation; Benefits: 401(k) match, medical, dental, vision, stock purchase plan
Skills & Requirements
Must-have
C++ development proficiency
UPF (Unified Power Format) implementation
Palladium and Protium platform experience
2-state and 4-state compilation flows
Verilog SystemVerilog VHDL familiarity
Nice-to-have
Perl Tcl/Tk Python scripting skills
High-performance data processing background
Collaboration with R&D and Product Engineering
Experience with IXCOM Modular Compiler
Knowledge of SAGE UPF debug tools
Key Requirements
Bachelor's degree in CS or EE with 7+ years experience