Senior Hardware Asic Arch/design Engineer

NXP

Ai inference chip architecture
Hardware-software co-optimization
Rtl design review and guidance
The role involves defining the product feature and capabilities for compute, memory, and high-speed interface subsystems in an AI inference chip

Job Summary

  • The role involves defining the product feature and capabilities for compute, memory, and high-speed interface subsystems in an AI inference chip.
  • Candidates will collaborate closely with software teams to co-optimize hardware features specifically for real-world AI inference workloads.
  • The position requires leading PPA analysis and trade-off discussions while ensuring consistency between architectural intent and timing/power goals.

Matching Summary

The role involves defining the product feature and capabilities for compute, memory, and high-speed interface subsystems in an AI inference chip.

Skills & Requirements

Must-have

  • AI inference chip architecture
  • Hardware-software co-optimization
  • RTL design review and guidance
  • PPA analysis and trade-offs
  • High-speed interface subsystems

Nice-to-have

  • Experience with quantization techniques
  • Knowledge of dataflow optimization
  • Understanding of sparsity in AI workloads
  • Strong simulation modeling skills
  • Debuggability and programmability focus

Key Requirements

  • Senior level experience in ASIC architecture
  • Deep understanding of AI inference workloads
  • Expertise in memory bandwidth bottlenecks

Work Rights

Not specified

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