Senior Physical Design Verification Layout Engineer

Invidia

Multiple Locations
Chip floorplan and pin placement
Physical verification methodology including erc lvs drc
Hands-on layout experience
NVIDIA is developing the industry's best high-speed communication devices delivering the highest throughput and lowest latency

Job Summary

  • NVIDIA is developing the industry's best high-speed communication devices delivering the highest throughput and lowest latency.
  • The role involves responsibility for chip floorplan, pin placement, physical verification flows, and physical layout implementation.
  • NVIDIA offers a meaningful, growing, and highly professional environment where engineers make a significant impact.

Matching Summary

NVIDIA is developing the industry's best high-speed communication devices delivering the highest throughput and lowest latency.

Skills & Requirements

Must-have

  • chip floorplan and pin placement
  • Physical Verification methodology including ERC LVS DRC
  • hands-on layout experience
  • advanced silicon process technologies knowledge
  • familiarity with Synopsys and Cadence EDA tools

Nice-to-have

  • Linux environment experience
  • TCL Python shell scripting abilities
  • data collection and analysis skills
  • AI tools orientation or willingness to learn
  • collaborative team player

Key Requirements

  • B.SC. or M.SC. in Electrical Engineering
  • 5+ years of layout experience
  • strong background in Physical Verification methodology
  • knowledge of advanced silicon process technologies

Work Rights

Not specified

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