Silicon Design Flow Methodology And Automation - Lec.
Indclutch
Penang, Malaysia
Logic equivalence check lec flows
Cadence conformal or synopsys formality
Atpg model gln generation
This role focuses on defining and maintaining scalable automation flows for Logic Equivalence Check and ATPG model generation across RTL to implementation stages
Job Summary
This role focuses on defining and maintaining scalable automation flows for Logic Equivalence Check and ATPG model generation across RTL to implementation stages.
Candidates must possess strong scripting skills in Tcl, Python, Perl, or shell to develop robust infrastructure for design verification.
The position requires close collaboration with DFT, ATPG, and physical design teams to ensure correctness and improve DFT coverage quality.
Matching Summary
This role focuses on defining and maintaining scalable automation flows for Logic Equivalence Check and ATPG model generation across RTL to implementation stages.