The role involves developing synthesizable RTL in Verilog or SystemVerilog for custom on-chip test and diagnostic IP targeting analog and mixed-signal failure detection
Job Summary
The role involves developing synthesizable RTL in Verilog or SystemVerilog for custom on-chip test and diagnostic IP targeting analog and mixed-signal failure detection.
Candidates will collaborate with cross-functional teams including analog designers, DFT engineers, and product teams to integrate diagnostic IP into complex SoC subsystems.
The position requires ensuring RTL is modular, timing-aware, and synthesis-friendly while supporting production test flows and firmware control requirements.
Matching Summary
Match Score: 85
The role involves developing synthesizable RTL in Verilog or SystemVerilog for custom on-chip test and diagnostic IP targeting analog and mixed-signal failure detection.
Skills & Requirements
Must-have
Verilog/SystemVerilog RTL design experience
ASIC SoC integration and verification
APB AHB AXI bus protocol knowledge
Digital logic block development
Fault injection and diagnostic testing
Nice-to-have
Analog mixed-signal behavioral modeling
Production screening test flow experience
Scripting for verification automation
Low-power design implementation awareness
Silicon debug support capabilities
Key Requirements
Bachelor's or Master's degree in Electrical Engineering
5-7 years of relevant ASIC design experience
Strong hands-on experience in RTL verification and debugging