Sta Cad/methodology Engineer

Cisco UK

Yerevan, Armenia
Hybrid
4+ years asic or soc design experience
Strong sta fundamentals in setup/hold timing
Proficiency in primetime or tempus tools
This hybrid role involves leading the development of scalable Static Timing Analysis flows and automation for Cisco's Silicon One team

Job Summary

  • This hybrid role involves leading the development of scalable Static Timing Analysis flows and automation for Cisco's Silicon One team.
  • The engineer will work hands-on with complex chip partitions, contributing to timing closure and issue triage alongside senior engineers.
  • Candidates will collaborate across RTL, DFT, and physical design teams to establish best practices for next-generation high-performance SoCs.

Matching Summary

This hybrid role involves leading the development of scalable Static Timing Analysis flows and automation for Cisco's Silicon One team.

Skills & Requirements

Must-have

  • 4+ years ASIC or SoC design experience
  • Strong STA fundamentals in setup/hold timing
  • Proficiency in PrimeTime or Tempus tools
  • Scripting skills in TCL and Python
  • Experience with SDC constraint development

Nice-to-have

  • Familiarity with physical design flows and synthesis
  • Experience with Unix/Linux development environments
  • Knowledge of EDA tool evaluation and deployment
  • Background in networking or communications domains
  • Collaborative attitude with strong communication skills

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • Minimum 4 years of experience in ASIC/SoC design
  • Solid understanding of MMMC analysis and OCV

Work Rights

Not specified

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