Principal Engineer, Analog Mixed-signal Ic Layout

Astera Labs

Bengaluru, India
On-site
High-speed analog ic layout
Cadence virtuoso
Chip top-level integration
Astera Labs is seeking a Principal Engineer for Analog Mixed-Signal IC Layout in Bengaluru, India, to lead the design of advanced Bi-CMOS/CMOS products. The role emphasizes collaboration within a cross-functional team and requires a strong background in high-speed analog IC layout and compliance with various design rules

Job Summary

  • You will play a critical role in designing advanced node Bi-CMOS / CMOS products.
  • You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout.
  • You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones.

Matching Summary

Match Score: 85

Astera Labs is seeking a Principal Engineer for Analog Mixed-Signal IC Layout in Bengaluru, India, to lead the design of advanced Bi-CMOS/CMOS products. The role emphasizes collaboration within a cross-functional team and requires a strong background in high-speed analog IC layout and compliance with various design rules.

Skills & Requirements

Must-have

  • high-speed analog IC layout
  • Cadence Virtuoso
  • chip top-level integration
  • block level layout design
  • minimizing layout parasitics
  • reduce skew and crosstalk
  • EM/IR compliance
  • DRC, LVS, ANT, density rules
  • ESD and latch-up design practices

Nice-to-have

  • BiCMOS layout experience
  • Cadence SKILL and TCL scripting

Key Requirements

  • Bachelor’s degree or advanced diploma in Electrical Engineering
  • 10+ years of experience in high-speed analog IC layout
  • Prior experience with BiCMOS layout
  • Proven experience handling at least one chip top-level through tapeout
  • Proficiency in layout extraction and parasitic analysis
  • Awareness of EMIR and antenna DRC rule-compliant layout practices

Work Rights

Not specified

Tailored Resume

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