Ic Design Verification Application Engineer

Cadence

San Jose, California, US
Base: $123,200 to $228,800; bonus/equity: incentiv...
Systemverilog, vhdl, verilog
Uvm testbench architecture
Rtl and testbench debug skills
Join an elite application engineering team for verification, working closely with industry-leading semiconductor and system companies to deploy Cadence’s market-leading verification platforms

Job Summary

  • Join an elite application engineering team for verification, working closely with industry-leading semiconductor and system companies to deploy Cadence’s market-leading verification platforms.
  • In this customer-facing role, you will provide front-line technical support in the pre- and post-sales process, owning customer success and developing innovative solutions.
  • By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools and unlock unique expertise in verification methodologies.

Matching Summary

Join an elite application engineering team for verification, working closely with industry-leading semiconductor and system companies to deploy Cadence’s market-leading verification platforms.

Salary

Base: $123,200 to $228,800; Bonus/Equity: Incentive compensation; Benefits: Paid vacation, 401(k), ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • SystemVerilog, VHDL, Verilog
  • UVM testbench architecture
  • RTL and Testbench debug skills
  • scripting (Perl, Python or Tcl)
  • software, HDL design and verification skills
  • analyze verification environments and design complexity

Nice-to-have

  • customer success ownership
  • AI assistants, Agentic AI, machine learning
  • technical presentations and product demonstrations
  • competitive landscape understanding
  • customer and R&D team interaction

Key Requirements

  • BS, MS, or PhD degree
  • 5+ years experience
  • Strong communication skills
  • Strong teamwork skills

Work Rights

Not specified

Tailored Resume

Cover Letter