Senior Design Verification Engineer

Altera Corporation

San Jose, California, United States
Base: $142.6k - $206.5k usd; bonus/equity: incenti...
Rtl verification and validation
Ip fpga validation and debugging
Systemverilog and uvm environments
Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios

Job Summary

  • Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.
  • Develop comprehensive verification and validation plans based on IP/FPGA architecture specifications, encompassing functional, system level, and hardware perspectives.
  • Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits.

Matching Summary

Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.

Salary

Base: $142.6k - $206.5k USD; Bonus/Equity: Incentive opportunities; Benefits: Not specified

Skills & Requirements

Must-have

  • RTL verification and validation
  • IP FPGA validation and debugging
  • SystemVerilog and UVM environments
  • High-level specification to test plan
  • Coverage driven random constraint environments
  • Debugging RTL design and testbench issues

Nice-to-have

  • Cross-functional team collaboration
  • Advanced verification techniques
  • Maximizing FPGA hardware capability

Key Requirements

  • BS/MS in Electrical Engineering or related field
  • 9+ years industry experience
  • 9+ years Verilog, SystemVerilog, UVM
  • 7+ years Ethernet/PCIe/CXL protocol verification
  • 7+ years UVM fluency
  • 7+ years complex coverage driven UVM
  • 7+ years high level specification to test plan
  • 7+ years debugging skills

Work Rights

Eligible for U.S. export authorizations

Tailored Resume

Cover Letter