Intel is seeking a Physical Design Lead for their Foundational IP Group in Penang, Malaysia. The role focuses on overseeing integration QA processes for foundational IP, enhancing QA coverage, and collaborating with various teams to implement best practices in design automation
Job Summary
The Foundational IP Integration QA Lead will oversee the FIP integration QA progress across all nodes and continuously improve QA coverage by identifying and filling gaps.
The team will improve efficiency by identifying and adopting best practices for QA automation and flows, working closely with DA engineers to specify automation requirements.
The role involves working on Full Chip Reference Design Development as the Timing Owner and driving technical collaboration with internal teams and EDA vendors.
Matching Summary
Match Score: 85
Intel is seeking a Physical Design Lead for their Foundational IP Group in Penang, Malaysia. The role focuses on overseeing integration QA processes for foundational IP, enhancing QA coverage, and collaborating with various teams to implement best practices in design automation.
Skills & Requirements
Must-have
Physical design flows
Static timing analysis
RTL to GDS cycle
Unix/Linux environments
Reliability verification processes
Nice-to-have
Advanced process nodes
Scripting languages PERL TCL
Team-oriented environment
High degree of ambiguity
Key Requirements
Bachelor of Science degree with 8 years of experience
Master's degree with 6 years of experience
Ph.D. with 4 years of experience
Proficiency in synthesis, place-and-route tools
Expertise in optimization, timing convergence, IR drop analysis