Asic Physical Design Engineer

Invidia

Shanghai, China
Physical design from rtl to gdsii
Sta for hierarchical design
Timing closure at chip level
You will work for the most advanced process/technology on the biggest chip in the world

Job Summary

  • You will work for the most advanced process/technology on the biggest chip in the world.
  • You will collaborate with experts across ASIC, P&R, DFT, SI, and architecture teams to drive physical friendly design.
  • You will develop and enhance the entire timing closure flow from frontend to backend including flow automation.

Matching Summary

You will work for the most advanced process/technology on the biggest chip in the world.

Skills & Requirements

Must-have

  • Physical design from RTL to GDSII
  • STA for hierarchical design
  • Timing closure at chip level
  • Synthesis and netlist quality check
  • Experience with Synopsys and Cadence EDA tools
  • Timing constraint creation and validation
  • Flow automation development

Nice-to-have

  • Proficient in Python, Perl or TCL
  • Excellent English communication skills
  • Experience driving physical friendly design with cross-functional teams

Key Requirements

  • MS in EE, CS or Microelectronics
  • 1+ year IC design implementation experience
  • Coursework in circuit and digital design
  • Proficient English reading and writing

Work Rights

Not specified

Tailored Resume

Cover Letter