Principal Engineer, Design Technology Co-optimization

Intel

Hillsboro, Oregon, US
$220,920.00-311,890.00 usd; not specified; not spe...
Hybrid
Advanced semiconductor technology
Foundation ip design
Standard cell library design
The Advanced Design & Foundational IP (ADFIP) organization focuses on design-technology co-optimization (DTCO), system-design co-optimization (STCO), and foundational IP development

Job Summary

  • The Advanced Design & Foundational IP (ADFIP) organization focuses on design-technology co-optimization (DTCO), system-design co-optimization (STCO), and foundational IP development.
  • As a logic library vertical lead, you will drive optimization of standard cell libraries on Intel's leading-edge process nodes and interface with key Intel foundry customers.
  • Intel offers a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and comprehensive benefits.

Matching Summary

The Advanced Design & Foundational IP (ADFIP) organization focuses on design-technology co-optimization (DTCO), system-design co-optimization (STCO), and foundational IP development.

Salary

$220,920.00-311,890.00 USD; Not specified; Not specified

Skills & Requirements

Must-have

  • advanced semiconductor technology
  • foundation IP design
  • standard cell library design
  • library cell characterization
  • semiconductor foundry ecosystem

Nice-to-have

  • product designs signoff methodology
  • pre and post Si foundry benchmarking
  • EDA tool design optimization
  • foundation IP Si validation

Key Requirements

  • 10+ years of industry experience
  • Ph.D. or master's degree in electrical engineering or computer science
  • Experience with library cell characterization methodology and tools
  • Experience with Spice circuit simulations

Work Rights

Not specified

Tailored Resume

Cover Letter