You will lead the end-to-end execution and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions
Job Summary
You will lead the end-to-end execution and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
This role offers the opportunity to build complex networking chips and collaborate directly with multiple teams including ASIC, Physical Design, CAD, Package Design, Software, DFT, and Architecture.
NVIDIA fosters a culture of creativity and autonomy, encouraging engineers to tackle challenges and become industry leaders.
Matching Summary
You will lead the end-to-end execution and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Skills & Requirements
Must-have
Chip-level CDC and RDC signoff
SystemVerilog RTL proficiency
Industry CDC/RDC tools expertise
Constraints and timing intent knowledge
Scripting with Python or TCL
Cross-team collaboration
Nice-to-have
Passion for quality
Experience with physical design delivery
Autonomous and creative engineering mindset
Strong teamwork skills
Key Requirements
B.Sc. or M.Sc. in Electrical or Computer Engineering
7+ years chip design experience
Experience with CDC/RDC tools like SpyGlass, Questa CDC, Real Intent
Proficiency in scripting languages such as Python, bash, Perl, or TCL