Sr. Principal Engineer -sta

NXP

Noida, India
Timing closure and signoff expertise
Advanced digital design architectures
Soc io constraints development
This role involves driving timing and convergence for SOC designs

Job Summary

  • This role involves driving timing and convergence for SOC designs.
  • The engineer will interface with critical domains like IP and DFT.
  • Hands-on experience with advanced technology nodes is essential.

Matching Summary

This role involves driving timing and convergence for SOC designs.

Skills & Requirements

Must-have

  • Timing closure and signoff expertise
  • Advanced digital design architectures
  • SOC IO constraints development

Nice-to-have

  • Experience with EDA tools
  • Knowledge of signal integrity
  • Scripting for design implementation

Key Requirements

  • Experience with technology nodes like 28nm to 7nm
  • Expertise in timing analysis and ECO creation
  • Ability to debug timing failures

Work Rights

Not specified

Tailored Resume

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