Senior Principal Design Engineer

Cadence

Systemverilog and uvm experience
Pcie functional verification background
7 to 15 years professional experience
Cadence is hiring motivated Verification Engineers to join their PCIe Design IP group

Job Summary

  • Cadence is hiring motivated Verification Engineers to join their PCIe Design IP group.
  • The role involves verifying PCIe Design IP across multiple generations using SystemVerilog and UVM.
  • Candidates will collaborate closely with design, architecture, and validation teams to ensure coverage closure.

Matching Summary

Cadence is hiring motivated Verification Engineers to join their PCIe Design IP group.

Skills & Requirements

Must-have

  • SystemVerilog and UVM experience
  • PCIe functional verification background
  • 7 to 15 years professional experience

Nice-to-have

  • Collaboration with design teams
  • Verification strategy development skills
  • Passion for technology innovation

Key Requirements

  • 7 to 15 years of experience
  • Strong hands-on SystemVerilog skills
  • Solid background in PCIe verification

Work Rights

Not specified

Tailored Resume

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