Technical Lead Digital Design Engineer

Astera Labs

San Jose, California, United States
Base: $160,000 to $195,000; bonus/equity: eligible...
On-site
Rtl implementation experience
Pcie gen 6/7 protocol expertise
Advanced cmos node production experience
This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure with direct impact on products deployed by leading hyperscalers

Job Summary

  • This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure with direct impact on products deployed by leading hyperscalers.
  • The successful candidate will own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification and physical design teams.
  • Astera Labs enables organizations to unlock the full potential of modern AI through purpose-built connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

Matching Summary

This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure with direct impact on products deployed by leading hyperscalers.

Salary

Base: $160,000 to $195,000; Bonus/Equity: Eligible for discretionary bonus and incentives; Benefits: Not specified

Skills & Requirements

Must-have

  • RTL implementation experience
  • PCIe Gen 6/7 protocol expertise
  • Advanced CMOS node production experience
  • Timing closure and DFT implementation
  • Micro-architecture definition skills

Nice-to-have

  • Firmware collaboration experience
  • RISC-V or Arm subsystem familiarity
  • CAD automation contributions
  • Data-center design delivery track record

Key Requirements

  • Bachelor's degree in Electrical Engineering
  • 5+ years hands-on SoC/silicon product experience
  • Production experience with advanced CMOS nodes ≤7nm

Work Rights

Not specified

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