Fpga Design Engineer (mtd, San Jose, Ca)

Teradyne, Inc.

San Jose, CA, United States
Base: $135,400 - $216,600; bonus/equity: discretio...
Digital design
Rtl coding
Static timing analysis

Salary

Base: $135,400 - $216,600; Bonus/Equity: Discretionary bonus based on financial performance; Benefits: Robust health and well-being programs

Skills & Requirements

Must-have

  • Digital Design
  • RTL coding
  • Static Timing Analysis
  • Digital Simulation
  • C or C++
  • Lab Equipment

Nice-to-have

  • FPGA Transceiver Design
  • DRAM and Flash Memory Interfaces
  • Altera/AMD Tool Flows
  • Verilog HDL
  • UVM Methodology
  • Scripting Languages
  • Linux and Windows

Key Requirements

  • Bachelor's Degree or equivalent with 5 years experience; Master's with 3 years
  • Experience with Digital Design and Architecture
  • Experience with Static Timing Analysis
  • Experience with Digital Simulation Testbench Creation
  • Experience with C or C++
  • Familiarity with Lab Equipment

Work Rights

Not specified

Tailored Resume

Cover Letter