Logic Design & Verification Engineer (RTL / UVM / ASIC Development)

DADACONSULTANTS PTE. LTD.

Singapore, Singapore
Not specified (assumed on-site based on location)
Rtl design using verilog/systemverilog
Asic/soc project experience
Functional verification and debugging
DADACONSULTANTS PTE. LTD. is seeking a Logic Design & Verification Engineer to join their fast-growing team in Singapore, focusing on ASIC development for large-scale computing applications. The role involves designing RTL modules, developing verification plans, and collaborating in a dynamic, engineering-driven environment

Job Summary

  • The role involves designing and implementing RTL modules for next-generation high-performance chip systems.
  • Engineers will develop verification plans and testbenches using UVM to ensure robust ASIC solutions.
  • Candidates will collaborate with architecture and physical design teams to support seamless SoC integration.

Matching Summary

Match Score: 85

DADACONSULTANTS PTE. LTD. is seeking a Logic Design & Verification Engineer to join their fast-growing team in Singapore, focusing on ASIC development for large-scale computing applications. The role involves designing RTL modules, developing verification plans, and collaborating in a dynamic, engineering-driven environment.

Skills & Requirements

Must-have

  • RTL design using Verilog/SystemVerilog
  • ASIC/SoC project experience
  • Functional verification and debugging
  • SoC integration and DFT participation

Nice-to-have

  • UVM methodology exposure
  • Python or Shell scripting skills
  • Collaborative engineering environment
  • Automation and tooling improvements

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • Understanding of digital design fundamentals
  • Basic scripting skills preferred

Work Rights

Not specified

Tailored Resume

Cover Letter