Senior Soc Timing Engineer

Altera Digital Health

Penang, Malaysia
Static timing analysis
Interface timing constraints
Timing signoff
The candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing

Job Summary

  • The candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
  • The role involves static timing analysis, deriving interface timing constraints, and final timing signoff.
  • Collaboration with design, architecture, and physical design teams is expected for timing convergence and closure.

Matching Summary

The candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.

Skills & Requirements

Must-have

  • Static Timing Analysis
  • Interface Timing Constraints
  • Timing Signoff
  • Primetime/PTPX
  • TCL, Python

Nice-to-have

  • Communication skills
  • Problem solving skills
  • Analytical skills

Key Requirements

  • 7+ Years’ experience timing closure and signoff
  • BE/MS/Phd in Electronics/Electrical Engineering
  • Experience in timing signoff in 10nm or lower technology

Work Rights

Not specified

Tailored Resume

Cover Letter