Memory Debug Engineer

Intel Corporation

Hillsboro, Oregon, United States
Base: $141,910.00-269,100.00 usd; bonus/equity: st...
On-site (location specified in hillsboro, oregon or folsom, california)
4+ years industry experience
Ddr4/ddr5 protocol expertise
High-speed oscilloscope usage
Intel Corporation is seeking a Memory Debug Engineer to join their Client Customer Engineering team, focusing on memory subsystem validation and debugging for next-generation Intel IA platforms. The ideal candidate will have substantial experience with memory protocols and debugging tools, contributing to the development of innovative technologies

Job Summary

  • This role drives the enablement, validation, and complex debugging of memory subsystems for next-generation Intel IA-based Mobile and Desktop platforms.
  • Candidates will provide strategic oversight of memory IO interfaces to ensure they meet rigorous electrical performance and stability standards at POR target frequencies.
  • The position offers a competitive total compensation package including stock bonuses, health benefits, retirement plans, and vacation time.

Matching Summary

Match Score: 85

Intel Corporation is seeking a Memory Debug Engineer to join their Client Customer Engineering team, focusing on memory subsystem validation and debugging for next-generation Intel IA platforms. The ideal candidate will have substantial experience with memory protocols and debugging tools, contributing to the development of innovative technologies.

Salary

Base: $141,910.00-269,100.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • 4+ years industry experience
  • DDR4/DDR5 protocol expertise
  • High-speed oscilloscope usage
  • Signal integrity compliance
  • MRC optimization skills

Nice-to-have

  • Python automation scripting
  • JEDEC committee participation
  • CXL standard familiarity
  • Intel System Debugger mastery
  • Executive communication skills

Key Requirements

  • BS/MS/PhD in Electrical or Computer Engineering
  • 3+ years DDR4/DDR5 physical layer experience
  • 3+ years debug tools proficiency
  • US work authorization required

Work Rights

Not specified

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