Group Director, Design Engineering - Front End

BETA CAE Systems International AG

Austin, United States
Rtl design in verilog
Microarchitectural features for ips
Pre-silicon verification activities
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment

Job Summary

  • Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
  • Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
  • Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Matching Summary

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

Skills & Requirements

Must-have

  • RTL design in Verilog
  • microarchitectural features for IPs
  • pre-silicon verification activities
  • cross-functional team collaboration
  • Synthesis, SDC creation

Nice-to-have

  • passion for innovation
  • good communication skills
  • design management skills
  • Cadence front end toolset

Key Requirements

  • 10+ years of Front End design/verification
  • BS/MS Engineering or Computer Sciences
  • leading and managing complex engineering projects
  • IP creation and/or SoC and IP integration
  • Expert in RTL design (Verilog)
  • Hands on Experience in Synthesis, SDC creation

Work Rights

Not specified

Tailored Resume

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