Asic Design Verification Engineer | Uvm | Exp. 8+ Years
Cisco UK
Uvm/system verilog proficiency
7+ years asic verification experience
Test bench development from scratch
The role involves architecting and developing industry-leading DV infrastructure for Cisco's unified Silicon One architecture used in core switching and routing products
Job Summary
The role involves architecting and developing industry-leading DV infrastructure for Cisco's unified Silicon One architecture used in core switching and routing products.
Candidates will lead the full verification lifecycle including block, cluster, and top-level environments with a focus on constraint random and directed stimulus testing.
This position offers dynamic collaboration with designers and software teams to ensure seamless integration and efficient performance during post-silicon bring-up.
Matching Summary
The role involves architecting and developing industry-leading DV infrastructure for Cisco's unified Silicon One architecture used in core switching and routing products.
Skills & Requirements
Must-have
UVM/System Verilog proficiency
7+ years ASIC verification experience
Test bench development from scratch
Perl or Python scripting skills
Block to top-level verification
Nice-to-have
Forwarding logic and P4 experience
Emulation platform knowledge (Veloce/Zebu)
Formal verification expertise
PCIe/Ethernet/RDMA protocol familiarity
Master's degree in EE/CE
Key Requirements
Bachelor's Degree in EE, CE, or related field
Minimum 7 years of ASIC design verification experience
Proficiency in System Verilog constraints, structures, and classes