Chiplet Physical Design Engineer

NVIDIA Corporation

Base: $168,000 - $264,500 (level 4) or $196,000 - ...
8+ years physical design experience
Bsee or msee degree required
High-speed ip integration expertise
The role involves owning the high-speed IP integration and building a Chiplet floorplan layout from early assembly through signoff

Job Summary

  • The role involves owning the high-speed IP integration and building a Chiplet floorplan layout from early assembly through signoff.
  • Candidates will work closely with partition owners and Full Chip STA engineers to ensure high quality and timely convergence.
  • NVIDIA offers competitive compensation ranging from $168,000 to $310,500 USD depending on level, along with equity and benefits.

Matching Summary

The role involves owning the high-speed IP integration and building a Chiplet floorplan layout from early assembly through signoff.

Salary

Base: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5); Bonus/Equity: Eligible for equity; Benefits: Comprehensive benefits package included

Skills & Requirements

Must-have

  • 8+ years physical design experience
  • BSEE or MSEE degree required
  • High-speed IP integration expertise
  • Full chip clock tree planning
  • DRC/LVS physical verification knowledge

Nice-to-have

  • Creative and autonomous engineer
  • Cross-business-unit teamwork skills
  • Experience with Synopsys or Cadence tools

Key Requirements

  • 8+ years in physical design
  • BSEE / MSEE or equivalent
  • Deep understanding of PNR and STA flows

Work Rights

Not specified

Tailored Resume

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