Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure
Job Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Key responsibilities include developing logic design, RTL coding, and simulation for IPs, applying optimization strategies to meet release requirements.
The role involves IP integration, release processes, hardware bring-up, verification, and failure debugging, requiring collaboration with different teams.
Matching Summary
Altera delivers cutting-edge FPGA, CPLD, and IP technologies, driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure.
Skills & Requirements
Must-have
RTL coding
logic design
IP development flow
System Verilog
VCS/Synopsys simulators
Lint and Synthesis
Nice-to-have
AI acceleration
next-generation data infrastructure
FPGA design and programming
RTL validation
hardware bring up
failure debugging
Key Requirements
15+ years' experience with bachelor's or master's degree
Experience in C/C++/Perl/Python/TCL/Unix Shell script