Sta Synthesis Engineer

Samsung Electronics

Bangalore, India
Sta fundamentals aocv pocv signal integrity
Full chip timing constraint development release
Primetime tempus eda tool experience
This role offers complete ownership of timing constraints at both image sensor full chip and subsystem levels

Job Summary

  • This role offers complete ownership of timing constraints at both image sensor full chip and subsystem levels.
  • Engineers will drive timing closure across diverse domains including RTL, DFT, and Physical Design teams.
  • The position requires developing scripts in TCL, Perl, or Python to improve efficiency in the ASIC back-end flow.

Matching Summary

This role offers complete ownership of timing constraints at both image sensor full chip and subsystem levels.

Skills & Requirements

Must-have

  • STA fundamentals AOCV POCV signal integrity
  • Full chip timing constraint development release
  • PrimeTime Tempus EDA tool experience
  • Physical and UPF aware synthesis expertise
  • TCL Python Perl scripting automation skills

Nice-to-have

  • UPF based static low power check experience
  • Power analysis at full chip level
  • Strong analytical and problem solving abilities
  • Ability to handle multiple project executions

Key Requirements

  • 4 to 7 years of relevant experience
  • B.Tech/B.E/M.Tech/M.E degree qualification
  • Hands-on experience with STA tools PrimeTime or Tempus

Work Rights

Not specified

Tailored Resume

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