Senior Principal Engineer, Design Verification

Marvell Technology

Base: cad 170,300 - 227,100 py; bonus/equity: not ...
15+ years digital design verification experience
Strong verilog systemverilog uvm knowledge
Object-oriented programming skills
This role involves leading the verification of major blocks or subsystems within advanced semiconductor solutions for AI and data infrastructure

Job Summary

  • This role involves leading the verification of major blocks or subsystems within advanced semiconductor solutions for AI and data infrastructure.
  • Candidates must possess a proven track record of managing complex SOC verification activities while meeting strict deadlines.
  • The position offers competitive compensation including a base pay range of CAD 170,300 to 227,100 per annum along with comprehensive benefits.

Matching Summary

Match Score: 85

This role involves leading the verification of major blocks or subsystems within advanced semiconductor solutions for AI and data infrastructure.

Salary

Base: CAD 170,300 - 227,100 per annum; Bonus/Equity: Not specified; Benefits: Competitive compensation and great benefits

Skills & Requirements

Must-have

  • 15+ years digital design verification experience
  • Strong Verilog SystemVerilog UVM knowledge
  • Object-oriented programming skills
  • Experience with Ethernet DDR HBM Security Networking
  • Block level test plan development

Nice-to-have

  • Technical mentoring of junior team members
  • Effective interpersonal and communication skills
  • Ability to work under tight schedule pressure
  • Collaboration with diverse design stakeholders

Key Requirements

  • BS/MS in EE/CS required
  • 15+ years hands-on experience in digital design verification
  • Eligibility to access export-controlled information as defined by US law

Work Rights

Must be eligible to access export-controlled information (US citizens, lawful permanent residents, or protected individuals)

Tailored Resume

Cover Letter