Full Chip Timing Modeling And Integration Engineer
Altera
Penang, Malaysia
Static timing analysis (sta)
Liberty verilog sdc formats
Soc development experience
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies
Job Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Candidates will collaborate with cross-functional teams to define timing modeling strategies, generate high-level models, and validate them against design constraints.
This position requires extensive experience in SoC development, Static Timing Analysis correlation with Spice, and script writing for design automation.
Matching Summary
The role involves developing timing methodologies and executing full-chip timing for next-generation FPGA products in advanced process technologies.
Skills & Requirements
Must-have
Static Timing Analysis (STA)
Liberty Verilog SDC formats
SoC development experience
Python and Tcl scripting
Advanced process node knowledge
AOCV POCV silicon modeling
Nice-to-have
Multi voltage domain experience
FPGA DDR PCIe architecture
DFT constraint management
Cross-functional negotiation skills
Proactive design issue intervention
Key Requirements
BS/MS Degree in Electrical or Computer Engineering