The role involves driving full-custom layout implementation of high-performance analog/mixed-signal circuits for next-generation SerDes IP
Job Summary
The role involves driving full-custom layout implementation of high-performance analog/mixed-signal circuits for next-generation SerDes IP.
Candidates will ensure silicon success by executing layout in advanced nodes such as 22nm, 12nm, and 6nm while managing signal integrity.
This position offers the opportunity to contribute to first-silicon success in a fast-paced startup environment focused on AI accelerators and chiplet systems.
Matching Summary
Match Score: 75
The role involves driving full-custom layout implementation of high-performance analog/mixed-signal circuits for next-generation SerDes IP.
Skills & Requirements
Must-have
Advanced process node layout experience
High-speed SerDes PHY design
Synopsys Custom Compiler or Cadence Virtuoso
DRC/LVS closure with Mentor Calibre
Parasitic extraction and post-layout optimization
Nice-to-have
Multi-Gbps SerDes PHY experience
Transmission line effects and impedance control
ESD design and IO layout expertise
Advanced packaging and chiplet technologies
EM/IR tools and reliability analysis
Key Requirements
Diploma or Bachelor's degree in Electrical/Electronic Engineering
Minimum 3 years of custom IC layout design experience
Proven experience in advanced nodes ≤28nm (preferably 22nm/12nm)