Design Verification Engineer/lead

Altera

Bengaluru, Karnataka, India
Advanced dv methodologies
System verilog hdl
Uvm
Plan, build, and execute the verification of new and existing features of Altera's FPGA Interface IPs, resulting in no bugs in the final design

Job Summary

  • Plan, build, and execute the verification of new and existing features of Altera's FPGA Interface IPs, resulting in no bugs in the final design.
  • Design and implement advanced verification environments, tools, and test-plans enabling first-pass silicon success.
  • Lead IP delivery to multiple customers while ensuring technical excellence and balancing competing requirements, schedules, and resources.

Matching Summary

Plan, build, and execute the verification of new and existing features of Altera's FPGA Interface IPs, resulting in no bugs in the final design.

Skills & Requirements

Must-have

  • advanced DV methodologies
  • System Verilog HDL
  • UVM
  • Python/TCL scripting
  • Ethernet and PCIe protocols

Nice-to-have

  • ML-based verification flows
  • formal verification techniques
  • emulation or FPGA based Verification
  • FPGA design flow knowledge

Key Requirements

  • B.Tech/M.Tech in Electronics Engineering
  • 10+ years of relevant experience
  • System Verilog/UVM coding proficiency
  • C/C++ programming
  • Shell/Python/TCL scripting

Work Rights

Not specified

Tailored Resume

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