Soc/fpga Design Verification Engineering Lead/manager

Altera Digital Health

Bengaluru, Karnataka, India
Ip and soc design verification
Leading silicon design verification processes
System verilog, constrained random verification
Lead/manage a team of design verification engineers responsible for IP and SoC design verification, deploying and managing leading silicon design verification processes, procedures, tools, and technologies

Job Summary

  • Lead/manage a team of design verification engineers responsible for IP and SoC design verification, deploying and managing leading silicon design verification processes, procedures, tools, and technologies.
  • Works with design, microarchitecture, and post-silicon validation teams to identify design bugs, improve overall microarchitecture, and collaborates with program leaders on verification delivery and regression metrics.
  • Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage and absorbs learning from post-silicon to update test plans for future products.

Matching Summary

Lead/manage a team of design verification engineers responsible for IP and SoC design verification, deploying and managing leading silicon design verification processes, procedures, tools, and technologies.

Skills & Requirements

Must-have

  • IP and SoC design verification
  • leading silicon design verification processes
  • System Verilog, constrained random verification
  • security-related testing
  • functional logic verification

Nice-to-have

  • improving overall microarchitecture
  • driving team results
  • inspiring people
  • role modeling Intel values
  • productive work environment

Key Requirements

  • 15+ years technical experience
  • BS, MS or PhD in Electrical or Computer Science Engineering
  • Pre Silicon Validation/Verification
  • OVM/UVM
  • TCL/PERL/Python scripting experience
  • Formal verification experience
  • Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping

Work Rights

Not specified

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