Senior Principal Switch Architect

Marvell Technology

Base: $177,380 - $265,700 py; bonus/equity: not sp...
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15+ years semiconductor architecture experience
Layer 2/layer 3 forwarding knowledge
C/c++ and python programming skills
** Marvell Technology is seeking a Senior Principal Switch Architect to lead the architecture of next-generation data center switch ASICs within their high-performance Teralynx Switch Architecture Team. The ideal candidate will have extensive experience in ASIC development, strong programming skills, and the ability to collaborate across multiple engineering disciplines. **

Job Summary

  • You will join the high-performance Teralynx Switch Architecture Team to define the architecture of Marvell's next-generation data center switch ASICs.
  • The role offers a deep, hands-on opportunity to shape silicon that scales to the next generation of cloud and AI data centers.
  • Marvell provides a stable environment with resources of a global leader paired with the agility of a fast-moving product organization.

Matching Summary

Match Score: 75

** Marvell Technology is seeking a Senior Principal Switch Architect to lead the architecture of next-generation data center switch ASICs within their high-performance Teralynx Switch Architecture Team. The ideal candidate will have extensive experience in ASIC development, strong programming skills, and the ability to collaborate across multiple engineering disciplines. **

Salary

Base: $177,380 - $265,700 per annum; Bonus/Equity: Not specified; Benefits: Flexible time off, 401k, year-end shutdown, floating holidays, volunteer PTO

Skills & Requirements

Must-have

  • 15+ years semiconductor architecture experience
  • Layer 2/Layer 3 forwarding knowledge
  • C/C++ and Python programming skills
  • ASIC design and validation expertise
  • Cross-functional technical leadership

Nice-to-have

  • Multi-die chiplet architecture experience
  • Customer-facing technical engagement
  • Published papers or patents
  • Standards body participation
  • Programmable datapath familiarity

Key Requirements

  • Bachelor's degree plus 15+ years experience OR Master's/PhD plus 10-12 years
  • Strong background in complex ASIC design
  • Eligibility to access export-controlled information under US law

Work Rights

Must be eligible to access export-controlled information (US citizens, lawful permanent residents, or protected individuals)

Tailored Resume

Cover Letter