Front End Asic Rtl/logic Verification Engineer

Altera Digital Health

Penang, Malaysia
Not specified
Rtl coding proficiency using hdl languages
Logic simulation and debug environment experience
Verification plan development skills
Altera Digital Health is seeking a Front End ASIC RTL/Logic Verification Engineer in Penang, Malaysia, to develop verification plans and ensure the correctness of design features. The ideal candidate should possess a strong educational background in Electronics Engineering and skills in communication, problem-solving, and RTL coding

Job Summary

  • The role involves developing comprehensive verification plans to ensure design features are correctly validated.
  • Candidates will support SoC customers to guarantee high-quality integration and verification of IP blocks.
  • The position requires driving quality assurance compliance to facilitate smooth IP-SoC handoffs.

Matching Summary

Match Score: 85

Altera Digital Health is seeking a Front End ASIC RTL/Logic Verification Engineer in Penang, Malaysia, to develop verification plans and ensure the correctness of design features. The ideal candidate should possess a strong educational background in Electronics Engineering and skills in communication, problem-solving, and RTL coding.

Skills & Requirements

Must-have

  • RTL coding proficiency using HDL languages
  • Logic simulation and debug environment experience
  • Verification plan development skills

Nice-to-have

  • Scripting knowledge advantage
  • Strong communication and leadership skills
  • Problem solving and analytical abilities

Key Requirements

  • BS/MS or PhD in Electronics Engineering
  • Proficiency with RTL coding and HDL languages

Work Rights

Not specified

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