Fpga Ip Verification Engineer

Indclutch

Bengaluru, India
On-site
Systemverilog and uvm
Verification environments
Python or perl scripting
Indclutch is seeking an FPGA IP Verification Engineer to design, develop, and validate software frameworks for FPGA applications, emphasizing collaboration with architects and design engineers. The ideal candidate should have extensive experience in ASIC or FPGA design verification, particularly with SystemVerilog and UVM, as well as strong scripting abilities

Job Summary

  • Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
  • Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
  • Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).

Matching Summary

Match Score: 85

Indclutch is seeking an FPGA IP Verification Engineer to design, develop, and validate software frameworks for FPGA applications, emphasizing collaboration with architects and design engineers. The ideal candidate should have extensive experience in ASIC or FPGA design verification, particularly with SystemVerilog and UVM, as well as strong scripting abilities.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • Verification environments
  • Python or Perl scripting
  • AMBA protocols
  • Coverage-driven verification

Nice-to-have

  • Collaborative team environment
  • Problem-solving skills
  • Communication skills

Key Requirements

  • 5+ years of experience
  • Bachelor's or Master's degree
  • ASIC or FPGA design verification experience
  • SystemVerilog Assertions (SVA)

Work Rights

Not specified

Tailored Resume

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