Senior Static Timing Analysis (sta) Developer

Altera Corporation

San Jose, California, United States
$178.9k - $259.0k usd; not specified; not specifie...
Sta algorithms and data structures
Large-scale eda software development
Performance-driven optimization
Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms

Job Summary

  • Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.
  • Identify and eliminate runtime bottlenecks, optimize PPA-critical components, and implement advanced data structures for extremely large IC designs.
  • Support customer tape-outs by ensuring STA robustness, accuracy, and runtime efficiency, and contribute to product roadmap discussions.

Matching Summary

Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.

Salary

$178.9K - $259.0K USD; Not specified; Not specified

Skills & Requirements

Must-have

  • STA algorithms and data structures
  • Large-scale EDA software development
  • Performance-driven optimization
  • C/C++ development skills
  • Multi-threading and memory optimization

Nice-to-have

  • Customer tape-out support
  • Disk-caching strategies
  • Distributed computing techniques

Key Requirements

  • 10+ years of experience in EDA software development
  • Strong C/C++ development skills
  • Experience with multi-threading
  • Experience with memory optimization
  • Experience with scalable software architecture

Work Rights

Eligible for U.S. export authorizations

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