Principal Application Engineer

Cadence

Physical design implementation experience
Asic design flow expertise
Hierarchical physical design strategies
The candidate will perform comprehensive physical design implementation including floor planning, power grid design, and timing closure for challenging low power and high speed designs

Job Summary

  • The candidate will perform comprehensive physical design implementation including floor planning, power grid design, and timing closure for challenging low power and high speed designs.
  • Responsibilities include leading next generation physical design methodology development and working closely with RTL design teams to ensure successful tapeouts.
  • Candidates must possess a BS/MS in EE/CS with at least three years of hands-on experience in physical design and verification at the latest technology nodes.

Matching Summary

The candidate will perform comprehensive physical design implementation including floor planning, power grid design, and timing closure for challenging low power and high speed designs.

Skills & Requirements

Must-have

  • Physical design implementation experience
  • ASIC design flow expertise
  • Hierarchical physical design strategies
  • Low power design knowledge
  • Static timing analysis and closure
  • EM/IR-Drop and crosstalk analysis
  • DRC/LVS/Antenna verification

Nice-to-have

  • Next generation methodology development
  • Hands-on technical leadership
  • Strong English communication skills
  • Self-motivated team player
  • Deep sub-micron technology issues understanding

Key Requirements

  • BS/MS in EE/CS required
  • 3+ years hands-on physical design experience
  • Solid knowledge of DFT and formal verification
  • Experience with P&R and DFM closure

Work Rights

Not specified

Tailored Resume

Cover Letter